Digital circuits within integrated circuit chips are often synchronized by one or more clock signals. Data is periodically stored in registers that are clocked by such clock signals. When data is not being evaluated, it is desirable to control or gate the clocks to unused circuitry in order to conserver power. Clock tree synthesis is thus important in assuring that data is captured when needed and that power is conserved when desired.
Traditional logic synthesis of register-transfer-logic (RTL) into Boolean logic gates provides little to no visibility into the consequences of logic implementation choices on clock synthesis. Clock synthesis is often considered at the end of the design even though decisions made in the front-end design flow of an integrated circuit may have significant consequences on the subsequent timing and power closure of the clock design and its clock tree.
Traditionally, clock signals are treated as ideal networks during logic synthesis and logic optimization. Physical information (e.g., driver size/strength, net widths, net lengths), buffering information (e.g., clock buffers, clock gating), or timing information (e.g., delay) is usually not estimated, or if estimated, not utilized during logic synthesis of other networks. It is usually during the back-end of the physical design of the overall integrated circuit design that clock synthesis occurs and any implementation details of the clock signals are explored.
For low power integrated circuit designs, estimating the costs of timing and power during automatic clock gate insertion is imprecise with such late clock synthesis. In lieu of reliable data, front-end designers typically focus on the gated flip-flop percentage. However, with the availability of advanced functional gating techniques, overly aggressive gating is an increasingly common result. Another negative consequence of clock synthesis occurring late in the design flow is the greater difficulty of grouping and cloning clock signals, such that it does not correspond to the physical netlist. With fewer clock signals grouped together, clock switching power may be greater. With clock synthesis occurring later in the design flow, it may be more difficult to obtain timing closure of the integrated circuit design during clock tree synthesis.
It is desirable to provide tools to the integrated circuit designer that are used earlier in the integrated circuit design flow to improve the synthesis of clock signal networks within an integrated circuit design.